![]() ![]() It would seem to me that if you would have a signal of sufficiently higher voltage than your I 2C bus voltage of 1.8 volts (3 volts or more), you could use NFETs (n-channel, enhancement-type mosfet, the 'normal' kind) to "cut" the SCL and SDL lines when the SoC has no power. If you want to take advantage of I 2C's zero leakage powerdown properties, you must either use only specific I 2C ports or convert a generic IO pin to an open collector (or open drain) -style arrangement somehow, cutting all current paths to the high side. I 2C compliant devices must use specific IO pads for the I 2C signals and they cannot have the high side driver, and I suspect pull-ups of any kind would be at least problematic. Can you check if the datasheet states such a condition for the pins? If it does, in reverse it means that the minimum for V CC in such an IC is the I 2C bus voltage minus 0.6 volts.Īs a consequence, microcontroller can have an I2C -style port (which is not I 2C logo certified), or use generic I/O pins to communicate with I 2C devices, but it is only logically compatible with I 2C when the microcontroller is powered up. Such pins have a V I,MAX condition of V CC+0.6 volts or such stated in the datasheet. But alas, a generic digital IO pin in a microcontroller or wherever, which can be driven high or low, cannot satisfy this condition.Ī push-pull digital pin has a P channel high side driver and protection structures connected to the power supply rail, which means that such a pin will always leak current towards the power supply rail if the voltage of that rail is less than the voltage at the pin, minus a diode's forward voltage. ![]() ![]() I 2C accomplishes this by being an open collector bus and open collector means that there is nothing pulling the data lines high inside a compliant IC. There is a specific point of importance here: the very nature of I 2C as a bus (and perhaps the only bus) specifically designed to allow zero leakage with one or more chips on the bus powered off. If that is negligible in your power budget then this might be a decent solution. And when the SoC is on, there will be additional leakage current through these, e.g. ![]() If the SoC is not powered, then this will be sufficient to ensure the lines are pulled to ground and the leakage in the controller input logic will be avoided. Make these weak, on the order of 100kohm. Here's an option that might avoid an isolator:Īdd external pull down resistors on the I2C lines to ground. If you check, the SoC supply is probably not at ground but is pulled up a little by the external pullups you added.īy "it consumes more power," are you referring only to the current in the pullup resistors or also to supply current of the controller IC? CMOS input logic needs to be driven at a supply or ground level to avoid drawing current (crowbar current or shoot-through current) that occurs when the input is somewhere between the supply and ground voltages. The leakage you are seeing is from the controller supply to the SoC I2C pins' ESD diodes to the SoC supply. And when the system is "off", you mean the SoC is off and the controller is on? From your comment that the I2C lines are in an undefined state, that appears to be the case (the SoC supply is off, so the I2C lines are no longer pulled up). When "on," are they both operating at the same voltage (what voltages)? Please clarify the power supply conditions for the SoC and the controller when both are on and when "the system is off." (I can't comment yet - not enough points, so this is more of a comment than an answer.) ![]()
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